1. Field
The disclosure relates to integrated circuit (IC) design, and more particularly, to the design of noise-cancelling receivers.
2. Background
In the design of radio-frequency (RF) communications receivers, it is generally desirable to provide a low-noise front-end to overcome noise contributions from subsequent stages of the receive chain. Certain receiver front ends employ a noise-cancelling architecture, wherein signal currents generated by two signal paths are weighted and summed together to cancel noise and out-of-band interference in the received signal. Such an architecture may advantageously relax the design requirements of the front-end amplifier and mixers in the receive chain.
In certain implementations, a noise-cancelling architecture may include capacitors coupled to the mixer outputs to bypass undesired differential mode signal components (e.g., due to local oscillator feed-through or out-of-band blockers) as well as common mode signal components (e.g., due to RF signal feed-through or harmonic components at twice the local oscillator frequency). However, providing such capacitors may undesirably lower the input impedance peaking frequency of a transimpedance amplifier (TIA) of the receive chain, as well as degrade TIA linearity in the presence of out-of-band blockers. Furthermore, the capacitors may undesirably consume a significant amount of on-chip area.
Accordingly, it would be desirable to provide techniques to improve the performance of noise-cancelling receiver front ends by improving out-of-band interferer rejection and receiver linearity.